Processor cache hits (data and instruction) are performance-wise extremely important. The TLB (translation lookaside buffer) is one of the most important CPU component as far as performance is concerned: it is a cache to the virtual to physical address translation process (the HP-UX Page Directory). As often showed, CPU accounts for a large part in SQL calls response times, of which most of it is memory access time. As threads move from one processor to the other, cache lines must be invalidated (if processor N°2 has to update a line loaded in a processor N°1 data cache), or at best reloaded when read access is required by both processors. I’ll write a post in the future about the in and outs of processor affinity. For now, I am interested by the rules that govern CPU switches, and understand what triggers them.
I’ll only consider versions more recent than HP-UX 11.11 :
The routine that does the load balancing is named mundane_balance()). This routine schedules itself into the timeout mechanism to be awakened once a second. It runs as an interruption service routine rather than within the context of another process. Thus it cannot be interrupted by some other event. Nor can it be starved by other real-time threads (it was call from stat_daemon() before 11.11).
A processor is in a state of starvation if it has one or more threads on its run queue that hasn’t executed for a long time (this “long time” varies with the CPU load). Only if there are no processors suffering from starvation, or all processors have starving threads (or could be forced into that condition), does HP-UX considers looking for balancing (see next post: HP-UX Processor Load Balancing on SMPs).